1. Field of the Invention
The invention relates to a memory address generator, more particularly to a memory address generator with scheduled write and read address generating capability and suitable for use when rearranging data.
2. Description of the Related Art
In a known motion video encoder, data obtained after a quantization operation are rearranged via a forward scanning operation, which may be carried out using zig-zag scanning (see FIG. 1) or alternate scanning (see FIG. 2), such that zero values can be grouped in succession to enhance the data compression effect using a variable length coder. Moreover, in a known motion video decoder, decoding of a compressed video bit stream is performed via a series of steps that include variable length decoding, inverse scanning, inverse quantization, inverse discrete cosine transformation, and motion compensation.
In a known memory control scheme for inverse scanning, after completing the writing of a variable length decoded data block into a memory device in a zig-zag or alternate scan arrangement (hereinafter referred to as non-raster scan arrangement), the data block is then read from the memory device in a raster scan arrangement, thereby resulting in the initial data sequence of the data block prior to forward scanning in the motion video encoder. However, because writing of the next data block into the memory device begins only after reading of the previous data block in the memory device has been completed, idling of decoder stages in the motion video decoder is encountered, and too much time is required to complete inverse scanning of a single data block.